【计算机组成与设计】Chisel取指和指令译码设计

extends App { (new chisel3.stage.ChiselStage).emitVerilog(new Decoder()) }  DecoderTest.scala import chiseltest chisel3.stage.ChiselStage).emitVerilog(new RegisterFile()) } RegisterTest.scala import chisel3._ import chiseltest Circuit extends App { (new chisel3.stage.ChiselStage).emitVerilog(new Circuit()) } Circuit.scala import chiseltest