问双向传输延迟的建模方法

EN

module bidi_delay #( parameter INERTIAL=0, TRANSPORT=10 ) (
    inout a, b
  );

  reg a2b, b2a;
  reg [23:0] a_strength, b_strength;

  always @(a) begin
    $sformat(a_strength, "%v", a);
    a2b <= #(TRANSPORT) (a_strength[23:16] == "S") ? a : 1'bz;
  end
  always @(b) begin
    $sformat(b_strength, "%v", b);
    b2a <= #(TRANSPORT) (b_strength[23:16] == "S") ? b : 1'bz;
  end

  assign (weak0,weak1) #(INERTIAL) a = b2a;
  assign (weak0,weak1) #(INERTIAL) b = a2b;
endmodule

module via_d (inout l, r, input bit en);
  timeunit 1ps;
  timeprecision 100fs;
  
  const bit[2:0] assoc_strn2int [bit[15:0]]='{ "Hi":0, "We":1, "Pu":2, "St":3, "Su":4};

  real d_l2r_ps;
  real d_r2l_ps; 
  bit l_internal_oe, r_internal_oe;

  bit[23:0] r_desc, l_desc, r_desc_dly, l_desc_dly, r_desc_inside, l_desc_inside;
  event l_stronger_drive_detected, r_stronger_drive_detected;

  initial {r_desc_dly,l_desc_dly} = {2{"HiZ"}};

  always @(r_desc_inside or l_desc_dly or r_stronger_drive_detected) 
    r_internal_oe <= oe_definition(l_desc_dly, r_desc, r_internal_oe);

  always @(l_desc_inside or r_desc_dly or l_stronger_drive_detected) 
    l_internal_oe <= oe_definition(r_desc_dly, l_desc, l_internal_oe);
  
  always @(l_desc_inside)
   l_desc_dly <= #(d_l2r_ps) l_desc_inside;

  always @(r_desc_inside)
    r_desc_dly <= #(d_r2l_ps) r_desc_inside;

  assign  r_desc_inside =  !r_internal_oe ? r_desc : "HiZ" ; 
  assign  l_desc_inside =  !l_internal_oe ? l_desc : "HiZ" ;

  always @(r_desc_dly[23:8] or l_desc[23:8])
    if((l_internal_oe == 1) & (r_desc_dly != l_desc))
      -> l_stronger_drive_detected;

  always @(l_desc_dly[23:8] or r_desc[23:8])
    if((r_internal_oe == 1) & (l_desc_dly != r_desc))
      -> r_stronger_drive_detected;

  always_comb if(en) $sformat(l_desc, "%v", l);
  always_comb if(en) $sformat(r_desc, "%v", r);

  via_strn_driver driver_l (r_desc_dly, l_internal_oe & en , l);
  via_strn_driver driver_r (l_desc_dly, r_internal_oe & en , r);

  function automatic bit oe_definition (bit[23:0] inside_desc, outside_desc, bit old_oe);
    oe_definition = inside_desc[23:8] == outside_desc[23:8] ? old_oe : 
      (assoc_strn2int[inside_desc[23:8]] > assoc_strn2int[outside_desc[23:8]]);
  endfunction

endmodule

module via_strn_driver(input bit [23:0] descr, bit en, output o);
  logic val ;
  always_comb begin
    case(descr[7:0])
      "1": val = 1'b1;
      "0": val = 1'b0;
      "X": val = 1'bx;
      "Z": val = 1'bz;
      default: $error(" Descr value is uncompatible with logic type"); 
    endcase  
  end

  assign (supply1,supply0) o = en ? ( descr[23:8] == "Su" ? val : 'z) : 'z;
  assign (strong1,strong0 )o = en ? ( descr[23:8] == "St" ? val : 'z) : 'z;
  assign (pull1,pull0)     o = en ? ( descr[23:8] == "Pu" ? val : 'z) : 'z;
  assign (weak1,weak0)     o = en ? ( descr[23:8] == "We" ? val : 'z) : 'z; 

endmodule