问modelSim VHDL某些输入信号未出现在目标窗口中

EN

inst_decoder : for i in 0 to MAX_BSIZE -1 generate

  signal llrs_valid_upper: std_logic ;
  signal llrs_in_upper : llrs_rec;
  signal llrs_valid_lower: std_logic;
  signal llrs_in_lower: llrs_rec;


begin


  -- get the corresponding llrs from the input_llr buffer, and set the llrs_valid to 1
  llrs_in_upper.system_llr <= input_llr(i); 
  llrs_in_upper.parity_llr <= input_llr(MAX_BSIZE+NUM_ENC_REGS+i);
  llrs_in_upper.extr_llr <= extr_upper_int(i);
  llrs_valid_upper <= input_llr_valid;

  inst_upper_algorithmic_block: component tcdec_algorithmic_block
    port map (
      clk => clk,
        rst => rst,
          en  => en_int,

          alpha_in => alpha_upper_int(i),
          beta_in => beta_upper_int(i+1),

          llrs_valid => llrs_valid_upper,
          llrs_in  => llrs_in_upper,

          init    => init,
          alpha_init => ALL_ZEROS,
          beta_init => ALL_ZEROS,

          extr_out  => extr_lower_int(de_il_table(i)),
          alpha_out => alpha_upper_int(i+1),
          beta_out => beta_upper_int(i)

    );

  llrs_in_lower.system_llr <= input_llr(il_table(i));
  llrs_in_lower.parity_llr <= input_llr(2*(MAX_BSIZE+NUM_ENC_REGS) + NUM_ENC_REGS + i);
  llrs_in_lower.extr_llr <= extr_lower_int(i);
  llrs_valid_lower <= input_llr_valid;

  inst_lower_algorithmic_block: component tcdec_algorithmic_block
    port map(
      clk => clk,
      rst => rst,
      en => en_int,

      alpha_in => alpha_lower_int(i),
      beta_in => beta_lower_int(i+1),

      llrs_valid => llrs_valid_lower,
      llrs_in => llrs_in_lower,

      init => init,
      alpha_init => ALL_ZEROS,
      beta_init => ALL_ZEROS,

      extr_out => extr_upper_int(il_table(i)),
      alpha_out => alpha_lower_int(i+1),
      beta_out => beta_lower_int(i)

    );  
end generate inst_decoder;